1. Field of the Invention
The present invention relates to a method for fabricating an array substrate. More particularly, the present invention relates to a method for manufacturing a thin film transistor (TFT) array substrate.
2. Description of Related Art
In general, a thin film transistor liquid crystal display (TFT-LCD) is primarily composed of a TFT array substrate, a color filter substrate, a liquid crystal layer, and a backlight module.
FIGS. 1A through 1F are flowcharts of a manufacturing process of a conventional TFT array substrate. In FIGS. 1A through 1F, only one set of pixels and pads is depicted for the purpose of explanation. As shown in FIG. 1A, a substrate 10 is provided at first, and a gate pattern 20, a first pad pattern 22, and a first electrode pattern 24 are formed on the substrate 10 with use of a first mask. Next, a gate insulation layer 30 and a semiconductor layer (not shown) are sequentially deposited on the substrate 10 for covering the gate pattern 20, the first pad pattern 22, and the first electrode pattern 24. After that, referring to FIG. 1B, a second mask is used for patterning the semiconductor layer, such that a channel layer 40 is formed on the gate insulation layer 30 above the corresponding gate pattern 20, and an ohmic contact layer 42 is selectively formed on the channel layer 40. Generally, a material of the channel layer 40 is amorphous silicon. Thereafter, referring to FIG. 1C, a third mask is used for forming a source pattern 50 and a drain pattern 60 on the channel layer 40 at respective sides of the gate pattern 20. Besides, a second electrode pattern 64 is formed on the gate insulation layer 30 above the corresponding first electrode pattern 24. As indicated in FIG. 1C, the ohmic contact layer 42 serves to reduce the contact resistance between the channel layer 40 and the source pattern 50 and between the channel layer 40 and the drain pattern 60. Additionally, the gate pattern 20, the channel layer 40, the source pattern 50, and the drain pattern 60 together constitute a TFT T, while the first electrode pattern 24, the gate insulation layer 30, and the second electrode pattern 64 together form a storage capacitor Cst having a metal-insulator-metal (MIM) structure.
After that, referring to FIG. 1D, a patterned passivation layer 70 is formed above the substrate 10. The patterned passivation layer 70 has a first opening H1, a second opening H2, and a third opening H3. The first opening H1 exposes a portion of the drain pattern 60. The second opening H2 and the third opening H3 respectively expose a portion of the gate insulation layer 30 above the corresponding first pad pattern 22 and a portion of the second electrode pattern 64.
Next, referring to FIG. 1E, an etching process is performed to remove the gate insulation layer 30 exposed by the second opening H2. As indicated in FIG. 1F, a fifth mask is then used to form a pixel electrode 80 and a second pad pattern 82 on the patterned passivation layer 70. It can be observed from FIG. 1F that the pixel electrode 80 is electrically connected to the drain pattern 60 through the first opening H1 and electrically connected to the second electrode pattern 64 through the third opening H3. The second pad pattern 82 is electrically connected to the first pad pattern 22 through the second opening H2. After the pixel electrode 80 and the second pad pattern 82 are entirely formed, the fabrication of a TFT array substrate 100 is completed.
However, referring to FIG. 1E, when a dry etching process is performed for removing the gate insulation layer 30 exposed by the second opening H2, an undercut effect is prone to occur in the gate insulation layer 30 around the second opening H2 as indicated in FIG. 1F′. Thereby, when a deposition process is subsequently performed, the second pad pattern 82 is likely to be disconnected to the first pad pattern 22, and signal transmission therebetween is negatively affected. On the other hand, when the gate insulation layer 30 within the second opening H2 is removed by performing the dry etching process, it is likely for an etching reaction gas to form unexpected by-products deposited at the first opening H1, thus posing an impact on the contact between the pixel electrode 80 and the drain pattern 60. Thereby, the contact resistance between the pixel electrode 80 and the drain pattern 60 is excessively high, or the signal transmission between the pixel electrode 80 and the drain pattern 60 fails because of the disconnection therebetween.
Moreover, when the gate insulation layer 30 above the first pad pattern 22 is removed by performing the dry etching process, high energy particles generated by plasma bombard a surface of the patterned passivation layer 70, such that the surface of the patterned passivation layer 70 is roughened, and a thickness of the patterned passivation layer 70 is reduced as well. Said phenomenon becomes worst when the patterned passivation layer 70 is made of an organic insulation material. As such, the overly roughened patterned passivation layer 70 having an uneven thickness deteriorates the performance of light transmission, thus giving rise to a mura effect and reducing a display quality of the TFT-LCD.
To resolve said issue, a conventional solution is proposed to perform an additional treatment step similar to a stripping process after the gate insulation layer 30 exposed by the second opening H2 is etched, so as to enhance the flatness of the patterned passivation layer 70. However, said additional treatment step relatively prolongs the fabrication of the TFT array substrate, results in a reduction of production, and brings about an increase in manufacturing costs.
FIGS. 2D through 2G are flowcharts of certain steps in a manufacturing process of another conventional TFT array substrate. A TFT array substrate 200 includes a storage capacitor Cst having a metal-insulator-ITO (MII) structure and comprising the first electrode pattern 24, the gate insulation layer 30, and the pixel electrode 80. The front-end manufacturing process of the TFT array substrate 200 is similar to that depicted in FIGS. 1A through 1C, while the back-end manufacturing process of the TFT array substrate 200 is illustrated in FIGS. 2D through 2G. As indicated in FIG. 2D, when the patterned passivation layer 70 is formed, not only the first opening H1 and the second opening H2 are formed with use of a half-tone mask, but also a first resist block 70A and a second resist block 70B with different thicknesses are formed above the first electrode pattern 24. Next, as shown in FIG. 2E, the gate insulation layer 30 within the second opening H2 is removed. Thereafter, as indicated in FIG. 2F, an ashing process is performed to remove the first resist block 70A having a relatively thin thickness, and a portion of the gate insulation layer 30 is exposed. After the implementation of the ashing process, a surface treatment step is performed on the patterned passivation layer 70 and a portion of the gate insulation layer 30. Here, the surface treatment step is often carried out by means of chemicals, e.g., a photoresist-striping liquid. With reference to FIG. 2G, the pixel electrode 80 and the second pad pattern 82 are then formed. Thereby, the first electrode pattern 24, the gate insulation layer 30, and the pixel electrode 80 in the TFT array substrate 200 together form the storage capacitor Cst having the MII structure.
Based on the above, in the process of manufacturing the TFT array substrate in which the storage capacitor has the M11 structure, one half-tone mask is required, and the ashing process is thereby necessitated for removing the relatively thin first resist block 70A in the passivation layer. Accordingly, the fabrication of the TFT array substrate is also prolonged, and the manufacturing costs of the TFT array substrate are increased as well.